A 2.5-V, 57-MHz, 15-Tap SC Bandpass Interpolating Filter with 320-Ms/s Output for DDFS system in 0.35-μm CMOS

With the utilization of the multirate sampling, both the channel selection and frequency uptranslation with simultaneous sampling rate increase is achieved by the proposed SwitchedCapacitor (SC) bandpass interpolating filter for an efficient Direct-Digital Frequency Synthesis (DDFS) system with the resulting dual rewards in the speed reduction to DDFS digital core plus Digital-to-Analog (DAC) as well as the order relaxation to the post continuous-time smoothing filter. This SC bandpass filter realizes 15-tap FIR, 57 MHz center frequency and >45 dB stopband rejection with translating 80 Ms/s, 22-24 MHz input signals to 56-58 MHz output at 320 MHz sampling rate (proper operation up to 400 Ms/s) in 0.35 μm CMOS. Specific multinotch FIR function, low-speed polyphase-based interpolation structure with Autozeroing, highspeed SC circuitry and opamp as well as ultra-low timing-skew multiple phase generation will be presented for achieving high-frequency, high-performance operations. The prototype IC’s exhibit 61 dB Signal-to-Noise and Distortion Ratio (SNDR), 69 dB for 1% THD and 61 dB for 1% IM3 dynamic range, and consume 2 mm active area, 120 and 16 mW power at a single 2.5V supply for analog and digital with corresponding to 8.6 mW analog power per zero.